Packaging capacity

Packaging capacity is the back-end ability to assemble finished AI processors — bonding logic dies and stacks of memory onto a shared base and turning loose components into a deployable accelerator. It is easy to overlook because attention fixates on the front-end wafer fabs, but a wafer is not a GPU until it is packaged. This assembly step is the gate every accelerator must pass through, and it has quietly become the explicit limiter on how many can ship, regardless of how much raw silicon exists upstream.

When packaging runs short, GPU availability is throttled and, downstream, so is training capacity — you can have the wafers and still not have the machines. A useful way to read it is that the bottleneck migrates: relieve packaging and the constraint simply moves to the next tightest link. The exposed club is specialised — TSMC does much of the advanced work in-house, while ASE and Amkor lead merchant assembly and Disco, Unimicron and Ibiden supply the tooling and substrates that make the step possible.