The AI supply chain, defined in plain English.

Dynamic RAM — the main working memory; HBM is a stacked, high-bandwidth form of it.

An enterprise SSD is a data-center-grade solid-state drive built on NAND flash for the endurance, capacity, and throughput that AI storage tiers demand.

High-Bandwidth Memory — DRAM stacked next to an accelerator to feed it data fast; often the real limit on GPU output.

How fast data can move per second — often the binding limit, not raw compute.

NAND flash is non-volatile memory that stores data without power, forming the bulk-storage tier for AI training datasets and model outputs.

Server DRAM is the standard high-speed working memory (today DDR5) that holds active data for CPUs and accelerators in data-center servers.

SRAM is fast on-chip memory built from transistors that holds a processor's caches and register files, sitting physically next to the compute logic.

An ABF substrate is the high-density circuit board built into a chip package that connects the silicon die to the outside world.

Assembling compute dies and memory into a finished, working chip — a real capacity bottleneck.

A chiplet is a small, specialized silicon die that is combined with other dies in one package instead of building a single large monolithic chip.

Chip-on-Wafer-on-Substrate — the advanced packaging that fuses compute dies and memory into one accelerator.

A die is the small rectangular piece of processed silicon, cut from a wafer, that forms the actual working chip.

Extreme-ultraviolet lithography — the leading-edge chip-printing tech, supplied by a single vendor.

A factory that manufactures chips designed by others; leading-edge capacity is scarce.

Hybrid bonding is an advanced technique that joins two chips directly with copper-to-copper connections, allowing far denser and faster links than traditional solder bumps.

An interposer is a thin base layer of silicon that sits under multiple chips and provides the dense, high-speed wiring that links them together.

Test and burn-in is the stage where every finished chip is exercised on automated equipment to confirm it works before it ships.

The share of chips on a wafer that work; low yield means fewer usable parts.

CMP (chemical mechanical planarization) is the process fabs use to grind and polish a wafer perfectly flat between chip-building steps.

DUV lithography is the deep-ultraviolet light-based printing process fabs use to pattern most chip layers, including mature and many mid-range advanced nodes.

EDA is the software used to design, simulate, and verify semiconductor chips before any silicon is manufactured.

Photoresist is the light-sensitive chemical coating fabs spread on a wafer so that a lithography tool can transfer a circuit pattern into it.

A process node is the generation of chipmaking technology — labeled in nanometers like 3nm or 2nm — that defines how small and dense a chip's transistors can be.

The reticle limit is the maximum area a lithography tool can print in a single exposure, which caps how large a single chip die can be.

A silicon wafer is the thin, mirror-polished disc of ultra-pure crystalline silicon that every semiconductor chip is printed on.

Specialty gases are the ultra-pure gases fabs use in etching, deposition, cleaning, and doping to build and shape the layers of a chip.

Tape-out is the milestone when a finished chip design is handed off to the foundry to be turned into physical silicon.

A wafer fab is the specialized factory where raw silicon wafers are processed into finished semiconductor chips.

Application-Specific Integrated Circuit — a custom chip built for one job, e.g. AI inference.

CUDA is NVIDIA's proprietary software platform that lets developers program its GPUs for general-purpose computing, including AI training and inference.

Floating-point operations per second — a raw measure of compute throughput.

Graphics Processing Unit — the massively-parallel chip that does most AI training and inference.

A host CPU is the general-purpose server processor that sits beside AI accelerators, feeding them data and running everything the accelerator does not.

An NPU (Neural Processing Unit) is a specialized accelerator built to run neural-network inference efficiently, from edge devices to data centers.

A superchip is a module that tightly fuses one or more GPUs with a CPU over a fast internal link so they act as a single, memory-coherent compute unit.

A tensor core is a specialized hardware unit inside a GPU that accelerates the matrix-multiply operations at the core of AI training and inference.

A TPU (Tensor Processing Unit) is a custom AI accelerator (ASIC) built specifically to run neural-network math rather than general-purpose computing.

A wafer-scale chip is a single processor built from an entire silicon wafer rather than being cut into many small dies.

An AI agent is software that wraps a language model so it can use tools, call APIs and take multiple steps on its own to complete a task.

A context window is the maximum amount of text, measured in tokens, that a model can consider at one time.

Fine-tuning is the post-training stage that specializes a pretrained model on a smaller, targeted dataset to shape its behavior.

Running a trained model to answer requests — the recurring cost of AI in production.

A KV cache is the stored key and value tensors from earlier tokens that let a language model generate each new token without recomputing the whole sequence.

Mixture of Experts (MoE) is a model architecture that activates only a few specialized sub-networks per input instead of the whole model.

Model distillation is a training technique in which a smaller student model learns to reproduce the behavior of a larger teacher model.

A multimodal model is an AI model that can understand and generate more than one kind of data, such as text, images, audio and video, within a single system.

Pretraining is the first and most compute-intensive stage of building an AI model, teaching it general skills from huge amounts of data.

Quantization is a technique that shrinks a model by storing and computing its numbers at lower numerical precision, such as FP8 or INT8.

RAG is a technique that lets an AI model answer using retrieved external documents rather than only what it learned in training.

A reasoning model is an AI model that spends extra compute at inference time to work through a problem step by step before giving a final answer.

The large, compute-heavy run that creates a base model from scratch.

1.6T optics are the next generation of optical transceiver modules, doubling the per-module data rate to 1.6 terabits per second.

800G optics are pluggable optical transceiver modules that move data across a data center at 800 gigabits per second.

AI Ethernet is standard Ethernet tuned for AI clusters, using RoCE to carry RDMA traffic with the low latency and near-zero loss that training needs.

Co-packaged optics places the optical components in the same package as the switch chip to cut the power and distance electrical signals must travel.

All-reduce is the collective communication step in which every chip in a cluster combines its partial results and ends up with the same final total — the core exchange that keeps distributed AI training in sync.

DWDM (dense wavelength-division multiplexing) is a technique that sends many separate data streams down one optical fiber at once, each carried on a slightly different wavelength, or color, of light.

A compound-semiconductor substrate behind high-speed photonics; supply is concentrated.

InfiniBand is a high-speed, low-latency networking standard used to connect servers and GPUs into a single AI training cluster.

Linear pluggable optics is a lower-power optical module design that removes the power-hungry DSP chip and drives the laser with a simpler analog signal path.

The high-speed network that ties accelerators together into a cluster.

NVLink is NVIDIA's high-speed interconnect that links GPUs directly so many chips can act as one tightly-coupled machine.

A module that converts electrical signals to light (and back) for optical links.

RDMA (remote direct memory access) lets one computer read from or write to another computer's memory directly over the network, bypassing the CPU and operating system to cut latency and overhead.

A retimer (or optical DSP) is a chip that cleans up and re-times a high-speed electrical signal; inside optical transceivers the DSP also encodes and recovers the data carried on light.

Connecting many machines into one cluster over a network fabric.

Serializer/Deserializer — the silicon that drives high-speed electrical links.

Silicon photonics is the practice of building optical parts — lasers, modulators, waveguides and detectors — on silicon chips using standard semiconductor manufacturing.

A spine-leaf network is a two-tier data-center wiring pattern in which every access ('leaf') switch connects to every core ('spine') switch, so any server can reach any other in a small, predictable number of hops.

A subsea cable is an undersea fiber-optic line laid across the ocean floor to carry data between continents — the physical backbone for the overwhelming majority of international internet traffic.

Switch silicon is the specialized ASIC inside a network switch that decides where each packet goes and forwards it between servers at line rate — the engine of the data-center fabric.

Behind-the-meter power is electricity generated on-site at a data center, on the customer's side of the utility meter, rather than drawn from the public grid.

BESS is a large-scale battery installation that stores electricity and discharges it on demand to balance supply, smooth peaks, and back up the grid.

Power Usage Effectiveness — total facility power divided by IT power; lower is more efficient.

The backlog of projects waiting to connect to the power grid — measured in years.

The interconnection queue is the waiting line of projects seeking approval and physical connection to the power grid before they can draw or deliver electricity.

Here, the electrical device that steps grid voltage down for a data center — in short supply.

A PPA is a long-term contract in which a data center or its operator agrees to buy electricity from a specific generator at a set price and volume for years at a time.

PUE is a data center's efficiency ratio — total facility power divided by the power that actually reaches the computing equipment.

Rack power density is the amount of electrical power — and therefore heat — packed into a single data-center rack, measured in kilowatts per rack.

An SMR is a compact nuclear reactor built from factory-made modules, designed to deliver firm, carbon-free power at a smaller scale than a conventional plant.

A substation is the electrical facility that steps high-voltage grid power down to usable levels for a data center, forming the physical handoff between the grid and the site.

WUE (Water Usage Effectiveness) measures how much water a data center consumes for cooling per unit of computing energy it delivers.

An AI factory is a data center designed and operated as a single large machine for producing AI, with power, cooling, networking, and accelerators engineered together.

Colocation is the business of leasing built-out, powered and cooled data-center space so tenants can install their own servers without owning the building.

Data-center construction is the physical build-out of AI data centers by specialized contractors, electricians and equipment vendors who turn announced capacity into operating floor space.

A high-density rack is a data-center rack engineered to hold far more powerful, hotter AI equipment — and to draw and dissipate far more power per rack than legacy servers.

Immersion cooling submerges servers directly in a non-conductive liquid that absorbs heat from every component at once, instead of using air or cold plates.

Liquid cooling uses circulating liquid, typically through cold plates on the chip, to carry heat away from AI accelerators far more efficiently than air.

Sovereign AI is the effort by governments to buy and build their own AI supercomputers and national AI clouds so that compute, data and models stay under domestic control.

AI capex is the capital spending on data centers, chips, power and networking needed to build and run AI systems.

The all-in price to generate model output — the convergence point of the whole stack.

GPU depreciation is the decline in an AI accelerator's value over its useful life as it wears and is superseded by faster chips, spreading its cost across the years it stays in service.

A hyperscaler is a very large cloud operator that builds and runs data centers at global scale to power its own AI and internet services and rent capacity to others.

The delay before a result arrives; low latency matters for interactive AI.

Model FLOPs Utilization is the fraction of a chip's peak arithmetic throughput that a training run actually uses.

A neocloud is a specialized cloud provider built to rent out large fleets of AI GPUs, focused purely on AI training and inference rather than general-purpose computing.

TCO is the full lifetime cost of running AI compute — hardware, power, cooling, networking, real estate and financing — not just the sticker price of the chips.

Throughput is the number of tokens an AI system can generate or process per second, a core measure of inference serving efficiency.

The unit of text an AI model reads or writes; pricing is per million tokens.