d-Matrix — AI supply-chain exposure

d-Matrix is a fabless designer of Corsair, an accelerator built around digital in-memory compute and a chiplet architecture, aimed squarely at low-latency serving of large language models. Rather than a general training chip, it targets the inference workload where responsiveness and cost-per-query dominate. It sits in the ASIC-producer layer and carries strategic weight through backing from Microsoft's M12 venture arm.

The real hook is architectural. Most accelerators are throttled by the bandwidth to feed data between memory and logic; d-Matrix attacks that wall by folding compute into the memory itself, a different answer to the same bottleneck high-bandwidth memory addresses by stacking. If it works at scale, it offers hyperscalers a cheaper way to run inference — and the M12 tie hints at a potential pull-through customer. The model places it as a differentiated challenger, not yet a load-bearing link.