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Layer 2 of 5

The AI chips layer

The compute silicon — and the memory, packaging and manufacturing behind it — that turns power into computation.

24 parts · 447 companies exposed

This is the most-watched layer of the AI chain and the most concentrated. At its centre is the accelerator itself, but the scarce steps are often elsewhere: the high-bandwidth memory (HBM) stacked beside the die, the advanced packaging (CoWoS and its cousins) that bonds them together, and the leading-edge foundry capacity that prints the logic — each run by a very small club of suppliers. Around them sits a supplier web most investors never see: silicon wafers, specialty process chemicals and gases, the ABF substrates a package is built on, test-and-burn-in capacity, and the EDA tools without which nothing gets designed. Because so few players can do the hardest steps at volume, this layer behaves like a stack of bottlenecks: when packaging or memory tightens, chip supply tightens with it regardless of how many wafers exist. The companies here range from the household accelerator names to the invisible suppliers whose capacity decides how many chips actually ship.

The parts in this layer

GPU
The main chip that does the heavy math for training and running AI models.
HBM
Super-fast memory stacked right next to AI chips so they are not starved for data.
Packaging capacity
The ability to assemble chips and memory together into a finished AI processor.
Lithography equipment
The machines that print chip patterns onto silicon wafers. One Dutch company, ASML, is the only maker of the most advanced kind (EUV) — nobody else in the world can build it.
Foundry capacity
The factory space available to actually manufacture advanced chips.
Hybrid bonding / 3D stacking
A way of stacking chips by welding their copper wiring directly together, with no solder bumps in between — so stacked dies sit closer and talk faster.
CoWoS / advanced packaging
A specific advanced method for placing chips and memory on a shared base.
Deposition & etch equipment
The machines that build a chip layer by layer — laying thin films down (deposition) and carving them away (etch). Three companies dominate the market.
EDA & design IP
The software and reusable building blocks engineers use to design chips before anything is manufactured.
Silicon wafer supply
The polished silicon discs every chip is printed on.
Metrology & inspection
The measurement and inspection machines that find microscopic defects while chips are being made — the quality-control eyes of every fab.
Process chemicals & gases
The ultra-pure chemicals and gases fabs consume every day to print and clean chips.
ASIC
A chip custom-built for one job, like a specific AI workload.
ABF substrates
The high-end circuit board inside a chip package that connects the silicon to the outside world.
Photomask & reticle
The master 'stencil' that a chip's circuit pattern is printed from — every wafer is exposed through it, so one flawed mask ruins everything printed after it.
Switch ASIC
The chip inside network switches that routes data between servers.
Chiplet interconnect (die-to-die)
The standardized 'plug' that lets separate chip tiles (chiplets) talk to each other inside one package — like USB, but between chips on the same substrate.
Test & burn-in capacity
The machines and time needed to verify every chip actually works before it ships.
SerDes
Tiny circuits that send data very fast over a single wire or fiber.
NAND & AI storage
The flash memory and hard drives that store the mountains of data AI trains on and produces.
Yield
The share of manufactured chips that come out good and usable.
Glass-core substrates
A new kind of package base made from glass instead of the plastic-like film used today — flatter and sturdier, so bigger, denser chip packages can be built.
DRAM
The regular fast memory used broadly across computers and servers.
Host compute (server CPUs)
The "normal" processors that sit next to AI chips in every server, feeding them data and running everything the accelerator does not.

Companies most exposed to this layer

  1. 1CoreWeave, Inc. logoCoreWeave, Inc.CRWVvia GPU98
  2. 23661.TWAlchip Technologies, Limited3661.TWvia ASIC95
  3. 3ASE Technology Holding Co., Ltd. logoASE Technology Holding Co., Ltd.ASXvia Packaging capacity95
  4. 4ASML logoASMLASMLvia Lithography equipment95
  5. 5Cadence Design Systems logoCadence Design SystemsCDNSvia EDA & design IP95
  6. 6KLA logoKLAKLACvia Metrology & inspection95
  7. 7NVIDIA logoNVIDIANVDAvia GPU95
  8. 8Synopsys logoSynopsysSNPSvia EDA & design IP95
  9. 9TSMC logoTSMCTSMvia Foundry capacity95
  10. 10Advantest Corporation logoAdvantest Corporation6857.Tvia HBM92
  11. 11Amkor Technology logoAmkor TechnologyAMKRvia Packaging capacity92
  12. 12Nebius Group N.V. logoNebius Group N.V.NBISvia GPU92
  13. 13SK hynix logoSK hynix000660.KSvia HBM92
  14. 14Ajinomoto logoAjinomoto2802.Tvia ABF substrates90
  15. 15AWEAlphawave SemiAWEvia SerDes90

+ 432 more companies exposed to this layer

Frequently asked

What is the AI chips layer?

The compute silicon — and the memory, packaging and manufacturing behind it — that turns power into computation.

What are the parts of the AI chips layer?

24 parts, including GPU, HBM, Packaging capacity, Lithography equipment, Foundry capacity, Hybrid bonding / 3D stacking. Each has its own page explaining what it is and who's exposed.

Which companies are most exposed to AI chips?

CoreWeave, Inc., Alchip Technologies, Limited, ASE Technology Holding Co., Ltd., ASML, Cadence Design Systems, KLA lead by modeled exposure — 447 companies in total touch this layer.

The other layers of the chain

EnergyInfrastructureModelsApplications

Model scores are illustrative reads from our model of the AI value chain — not investment advice.

as of 2026-07-17Medium confidence model v0.7.0
The whole chain